The present disclosure relates to increasing memory operating frequency, and in particular to providing a solar bit line and earlier latch points, or dynamic-to-static conversion points, to increase a latch margin of an output latch of a memory array and to reduce the dynamic pulse widths required for memory operations.
As the size of memory circuits continues to decrease, the wiring to and from memory cells continues to decrease in width and thickness and the distance between the wires also decreases. The decrease in width and thickness may result in an increased resistance, and the decrease in distance between wires may result in an increased capacitance along the wire. The resistances and capacitances may generate a delay along the wiring, particularly when memory cells farthest from an output line are accessed.
In addition, individual devices that make up arrays of memory cells and the supporting logic circuitry may suffer from signal loss between a memory cell array and an output signal line. To read data from a memory cell device, a pulse of a predetermined width may be applied to a word line, resulting in a corresponding pulse to be output from a desired memory cell. The pulse may propagate along a local bit line connected to a plurality of memory cells and a global bit line connected to a plurality of local bit lines through local evaluation logic. The resulting pulse may need to be detected and latched in a particular window, such as an output latch window, or a time that an output latch is asserted to latch a signal from the memory cells arrays.
However, with each level of signal propagation, such as from the word line through the transistors of the memory cell, from the memory cell to the local bit line, and from the local bit line to a global bit line via a logic gate, the pulse may shrink due to variable electrical characteristics of the circuitry. For example, a switching delay of a transistor in a memory cell and subsequent logic may decrease or delay the switching of the leading edge of the pulse, and a pre-charge circuit connected to a global bit line may cause a premature switching of a trailing edge of the pulse. Accordingly, the delays caused by circuit design characteristics and the pulse distortion due to circuit elements may result in a pulse along a global bit line having a narrower width than the word line pulse, and if the shrunken pulse is too narrow and/or if the delay is too great, the output latch of the memory circuit may not be able to latch the asserted state of the pulse. The nominal pulses associated with memory operations must be designed wide enough to account for data propagation variations and pulse distortion in order to reliably perform operations, such as reading the memory cell array. The widths of these dynamic signals may limit the data processing frequency of the memory.